1. Field of the Invention
This invention relates to an integrated circuit bipolar CMOS emitter-coupled logic gate with FET delay regulating elements.
2. Description of the Prior Art
As will be appreciated by those skilled in the art, the delay introduced by an integrated circuit logic gate may vary from chip to chip or even from one region on a single chip to another region on the same chip. Various factors can cause such gate delay variations between ostensibly identical gates. These factors include power supply variations, manufacturing process variations, temperature variations and the like.
As digital system technology progresses, both the cycle time of digital systems, and the individual delay introduced by logic circuits within the system, become shorter and shorter. Any tolerance for variations in logic circuit delay is a significant factor in limiting overall system performance.
U.S. Pat. Nos. 4,346,343 and 4,383,216, assigned to the assignee of this application, disclose an on-chip delay regulator circuit that varies the power in a logic circuit to minimize delay variations of the type described above. This delay regulator compares a periodic reference to an on-chip generated periodic signal sensitive to the factors that can cause variations in circuit delay. The comparison generates an error signal that is used to vary the power to the circuit. Increasing or decreasing the circuit power, increases or decreases the circuit speed, as necessary, to maintain a relatively constant circuit speed on each chip or in each region of a single chip.